Reconfiguring storage modes in a memory

ABSTRACT

A memory which is capable of reconfiguration between a first mode in which each storage cell is capable of storing a pair of data bits and a second mode in which each storage cell is capable of storing a single data. A memory according to the present teachings includes a storage cell having a first structure and a second structure each capable of a storage state and mechanisms for reconfiguring the memory between a first mode in which the storage states of the first and second structures indicate a first and a second data bit, respectively, and a second mode in which the storage states combine to indicate a data bit.

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The present invention pertains to the field of random accessmemories. More particularly, this invention relates to storage modes ina memory.

[0003] 2. Art Background

[0004] A random access memory typically includes an array of storagecells. Each storage cell typically includes structures capable ofchanging storage states. For example, ferroelectric random accessmemories (FeRAMs) typically include ferroelectric capacitors capable ofchanging charge polarities. In another example, magnetic random accessmemories (MRAMs) commonly include magnetic films capable of changingmagnetizations. The storage states of a storage cell usually indicateits logic state, i.e. a value of a bit that it stores.

[0005] Some memories implement a storage cell having a single storagestructure capable of changing storage states. For example, a storagecell in a ferroelectric random access memory (FeRAM) may include asingle ferroelectric capacitor capable of changing its charge polarityand a single transistor for accessing the stored state. Such a structuremay be referred to as a one-transistor-one-capacitor (1T1C) cellstructure. Similarly, an MRAM storage cell may be implemented with asingle magnetic film structure capable of changing its magnetization.

[0006] A storage cell having a single storage structure is usually readby sensing its storage state and comparing the obtained signal to areference. Typically, the reference is common for all the storage cellsin a memory. If a signal sensed from a storage cell is greater than thereference then the storage cell is usually deemed to be in a first logicstate and if the sensed signal is less than the reference then thestorage cell is usually deemed to be in a second logic state.

[0007] The characteristics of the storage states in the storage cells ofa memory typically vary due to variation in a manufacturing process aswell as material fatigue over time and other factors. A relatively highvariation in storage state characteristics usually increases thedifficulty in selecting a reference which is suitable for reading all ofthe storage cells in a memory. If the variation among storage cells in amemory is large enough then a suitable reference may not be obtainable.Unfortunately, in such cases and the memory is usually discarded. Suchdiscarding of individual memories usually decreases the yield of amanufacturing process and increases overall manufacturing costs.

[0008] Other memories implement a storage cell having dual storagestructures each capable of changing storage states. For example, astorage cell in an FeRAM may include a pair of ferroelectric capacitorseach capable of changing its charge polarity and a pair of correspondingtransistors for accessing the stored states. Such a structure may bereferred to as a two-transistor-two-capacitor (2T2C) cell structure.Similarly, an MRAM storage cell may be implemented with dual magneticfilm structures each capable of changing its magnetization.

[0009] A storage cell having dual storage structures is usually read bysensing both its storage states and performing a differential comparisonon the sensed signals. Such memories are usually less susceptible to theproblems caused by manufacturing variation and material fatigue etc.,because such variation tend to influence the storage structures in acomplementary fashion. Such storage cells however, limit the amount ofdata storage density in a memory due to the additional storagestructures.

SUMMARY OF THE INVENTION

[0010] A memory is disclosed which is capable of reconfiguration betweena first mode in which each storage cell is capable of storing a pair ofdata bits and a second mode in which each storage cell is capable ofstoring a single data. A memory according to the present teachingsincludes a storage cell having a first structure and a second structureeach capable of a storage state and mechanisms for reconfiguring thememory between a first mode in which the storage states of the first andsecond structures indicate a first and a second data bit, respectively,and a second mode in which the storage states combine to indicate a databit. The present techniques enable reconfiguration of the memory at thetime of manufacture or at a later time in response to measuredcharacteristics of the storage cells.

[0011] Other features and advantages of the present invention will beapparent from the detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention is described with respect to particularexemplary embodiments thereof and reference is accordingly made to thedrawings in which:

[0013]FIG. 1 shows a memory according to the present teachings;

[0014]FIGS. 2a-2 b show example charge distributions for a memory;

[0015]FIG. 3 shows one embodiment of a storage cell which include a pairof ferrorelectric capacitors as charge storage structures.

DETAILED DESCRIPTION

[0016]FIG. 1 shows a memory 10 according to the present teachings. Thememory 10 is shown having a storage cell 20 coupled to a set of bitlines 30-32 and a set of word lines 40-42. The bit lines 30-32 arecoupled to a sense amplifier 16 which provides an indication 50 of thelogic state of the storage cell 10 during a read operation.

[0017] A memory according to the present teachings may include anynumber of storage cells, for an example an array, with appropriatearrangement of additional bit lines and word lines, etc.

[0018] The storage cell 20 includes a pair of storage structures eachcapable of changing storage states. The storage cell 20 is capable ofoperating in a first mode in which the respective storage states of itstwo storage structures indicate a first and a second data bit. Thestorage cell 20 is further capable of operating in a second mode inwhich the storage states of its two storage structures combine toindicate a data bit. The operating mode of the storage cell 20 iscontrolled by an access circuit 12.

[0019] The access circuit 12 in this embodiment includes a non-volatilememory 14 that stores an indication of the operating mode. Thenon-volatile memory 14 may hold a single indication of the operatingmode of all the storage cells in the memory 10 or different indicationsof operating mode for different storage cells or groups of storagecells. The contents of the non-volatile memory 14 may be programmedduring manufacture of the memory 10 or at a later time. The contents ofthe non-volatile memory 14 may be programmed and/or reprogrammed by anexternal processor (not shown).

[0020] In one embodiment, the non-volatile memory 14 is a set of FeRAMstorage cells. In other embodiments, other types of non-volatile storagemechanisms may be used.

[0021] In the first mode of operation, the access circuit 12 reads thecontents of one half of the storage cell 20, i.e. the state of its firststorage structure, by applying a voltage V_(DD) to the word line 40 andby applying a voltage V₀ to the word line 42 and by applying a referencevoltage V_(REF) to the bit line 32. The voltage V_(DD) on the word line40 causes a charge to be read out of the first storage structure in thestorage cell 20 onto the bit line 30. The voltage V₀ one the word line42 prevents charge from being read out of the second storage structurein the storage cell 20 onto the bit line 32. The reference voltageV_(REF) instead drives the bit line 32. The sense amplifier 16 comparesthe voltage read out onto the bit line 30 to the reference voltageV_(REF) carried on the bit line 32, thereby yielding the indication 50of the logic state of one half of the storage cell 20. The contents ofthe other half of the storage cell 20, i.e. the state of its secondstorage structure, may be read in a similar manner by reversing theactivity on the word lines 40 and 42.

[0022] In the second mode of operation, the access circuit 12 reads thestorage cell 20 by applying the voltage V_(DD) to the word lines 40 and42 and by not driving the bit line 32. The voltage V_(DD) on the wordline 40 causes a charge to be read out of the first storage structure inthe storage cell 20 onto the bit line 30. The voltage V_(DD) one theword line 42 causes a charge to be read out of the second storagestructure in the storage cell 20 onto the bit line 32. The senseamplifier 16 compares the voltage read out onto the bit line 30 to thevoltage read out onto the bit line 32, thereby yielding the indication50 of the logic state of the storage cell 20.

[0023] In one embodiment, the voltage V_(DD) is a supply voltage for thememory 10 and the voltage V₀ is zero volts.

[0024]FIG. 2a shows a charge distribution obtained for an embodiment ofthe memory 10 which includes a relatively large number of storage cells.The charge distribution shows the number of storage cells verses storedcharge in the storage structures of a storage cell. The left portion ofthe distribution may be deemed as charge levels corresponding to a “0”logic state of a storage cell and the right portion of the distributionmay be deemed as charge levels corresponding to a “1” logic state of astorage cell.

[0025] A memory having the charge distribution shown in FIG. 2a is wellsuited for operation in the first mode because a level for V_(REF) maybe determined that will clearly distinguish the storage state of all ofits memory cells during read operations.

[0026]FIG. 2b shows another example of a charge distribution. A memoryhaving this charge distribution is better suited for operation in thesecond mode because of the difficulty in determining a level for V_(REF)that will clearly distinguish the storage state of all of its memorycells during read operations. Any level for V_(REF) chosen will likelylead to failures particularly with time as individual cells age andcharge characteristics drift.

[0027] The memory 10 may undergo tests that determine its chargedistribution at the time of its manufacture or at a later time such asduring a repair. The charge distribution is analyzed to determinewhether the memory 10 should be operated in the first mode or in thesecond mode. The non-volatile memory 14 may then be programmed orreprogrammed accordingly.

[0028]FIG. 3 shows one embodiment of the storage cell 20 which include apair of ferrorelectric capacitors C0 and C1 as storage structures. Thememory 10 in this embodiment is a ferroelectric random access memory(FeRAM). The FeRAM storage cell 20 may be viewed as beingre-programmable between 1T1C and 2T2C configurations. The presentteachings are nevertheless applicable to other types of memories thatemploy other types of storage structures such as MRAMs.

[0029] The ferrorelectric capacitor C0 enables storage of a chargepolarity in the first mode of operation and the ferrorelectric capacitorC1 enables storage of a complementary charge polarity in the second modeof operation. The storage cell 20 includes an access transistor M0 fortransferring charge from the ferroelectric capacitor C0 to the bit line30 and an access transistor M1 for transferring charge from theferroelectric capacitor C1 to the bit line 32.

[0030] The ferrorelectric capacitors C0 and C1 are coupled to a plateline 60 which is driven by the access circuit 12 and charges are writteninto the ferrorelectric capacitors C0 and C1 in a known manner.

[0031] The foregoing detailed description of the present invention isprovided for the purposes of illustration and is not intended to beexhaustive or to limit the invention to the precise embodimentdisclosed. Accordingly, the scope of the present invention is defined bythe appended claims.

What is claimed is:
 1. A memory, comprising: storage cell having a first structure and a second structure each capable of a storage state; means for reconfiguring the memory between a first mode in which the storage states of the first and second structures indicate a first and a second data bit, respectively, and a second mode in which the storage states combine to indicate a data bit.
 2. The memory of claim 1, wherein the first structure includes a capacitor capable of the corresponding storage state.
 3. The memory of claim 2, wherein the capacitor is a ferroelectric capacitor.
 4. The memory of claim 1, wherein the second structure includes a capacitor capable of the corresponding storage state.
 5. The memory of claim 4, wherein the capacitor is a ferroelectric capacitor.
 6. The memory of claim 1, further comprising means for storing an indication of the first or the second mode.
 7. The memory of claim 6, wherein the means for storing an indication comprises a non-volatile memory.
 8. The memory of claim 6, wherein the non-volatile memory comprises a set of ferroelectric storage cells.
 9. The memory of claim 1, further comprising a sense amplifier for determining the storage states.
 10. The memory of claim 9, wherein the means for reconfiguring includes an access circuit coupled to a pair of bit lines and a pair of word lines of the storage cell.
 11. The memory of claim 10, wherein the access circuit reads the storage cell in the first mode by applying a set of voltages to the bit and word lines such that the sense amplifier compares the storage state of the first structure to a reference.
 12. The memory of claim 10, wherein the access circuit reads the storage cell in the second mode by applying a set of voltages to the bit and word lines such that the sense amplifier compares the storage states of the first and second structures.
 13. A method for reconfiguring a storage mode of a memory, comprising the steps of: determining whether a reference for reading a set of storage cells in the memory is obtainable; if the reference is obtainable, then programming the memory into a first mode in which each storage cell is capable of storing a pair of data bits; if the reference is not obtainable, then programming the memory into a second mode in which each storage cell is capable of storing a single data bit.
 14. The method of claim 13, wherein the step of determining whether a reference is obtainable comprises the step of determining whether the reference is obtainable in response to a charge distribution for the memory.
 15. The method of claim 13, wherein the steps of programming comprise the step of programming a set of non-volatile memory cells in the memory. 